The present invention relates broadly to a discharge protection apparatus, and in particular to an electrostatic discharge protective apparatus for integrated circuits.
The state of the art of electrostatic discharge protective apparatus is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. Patents:
U.S. Pat. No. 4,752,862 issued to Takahashi et al on Jun. 21, 1988; PA0 U.S. Pat. No. 4,791,524 issued to Teigen et al on Dec. 13, 1988; PA0 U.S. Pat. No. 4,821,320 issued to Andert et al on Apr. 11, 1989; PA0 U.S. Pat. No. 4,864,458 issued to Demorat et al on Sep. 5, 1989; PA0 U.S. Pat. No. 4,889,750 issued to Wiley on Dec. 26, 1989; and PA0 U.S. Pat. No. 4,958,255 issued to Pritchard on Sep. 18, 1990.
The Takahashi et al patent discloses an electronic device that has immunity against the phenomena of static electricity which comprises a metal housing containing an electronic circuit which maintains an ordinary potential of the input line by inducing a pull potential on the input line of the electronic circuit network in order to eliminate the induction of active potentials other than an active potential for operating the device, thereby to prevent erroneous inputs from entering thereto.
The Teigen et al patent describes electrostatic discharge for electronic packages comprising a circuit card which has a conductive bracket (or frame or cover) which contacts the conductive frame (or cage or enclosure) of an assembly before the circuit can electrically connect to a bus or other circuit in the assembly. A high-value resistor between circuit ground and the bracket allows static charge to dissipate to frame ground harmlessly.
The Andert et al patent discloses a device for protecting both the operator of an electronic apparatus and the electronic equipment of the apparatus when the operator carries a high electrostatic charge. To ensure a gentle electrostatic discharge of the operator, resistance paths which lead to a ground point of the electronic apparatus are arranged in the danger zone of the apparatus.
The Demorat Jr. et al patent is directed to a switching device on a printed circuit card assembly which permits the signal ground of the printed circuit card to be grounded to the machine ground during insertion of the card into the frame of the machine, and when the card is fully inserted the switch is opened to allow the signal ground of the card to be electrically isolated from the machine ground of the frame.
The Wiley patent describes coatings and foams which are useful in providing a conductive layer on a surface to provide protection against harmful electrostatic discharges, and are also useful in absorbing and dissipating mechanical and electromagnetic energy and preventing electrostatic build-up; these compositions also provide electromagnetic compatibility.
The Pritchard patent discusses a protection circuit which connects differentiated grounds in an electronic system either by a single diode, or by two diodes arranged in a back-to-back, parallel fashion. The differential grounds may include a chasis ground, a logic ground and an earth ground. The circuit locally connects two of the differentiated grounds, thereby providing a low inductance path for the fast discharging of electrostatic charge build-ups.
Integrated circuits are generally provided with some sort of electrostatic discharge (ESD) protective circuit for each input bonding pad. It is also fairly common to design outputs either in such a way that they are inherently resistant to electrostatic discharge or to provide them, also, with a protective circuit. These pads will be referred to as input/output pads, (I/O). While the above description is general, it is particularly descriptive of digital inputs and outputs. The circuits which are presently used, incorporate devices which have extremely non-linear voltage characteristics to establish a connection between the protected input or output and either a "ground" or a "power supply" lead(s). The non-linearity is such that a voltage within the normal operating range of the input/output pads will result in a negligible current through the device, but a larger voltage applied will result in sufficient current being drawn that a small series impedance will limit the voltage "seen" by following circuits. There are two consequences to providing electrostatic discharge protection in that way: 1) There is a time delay between the time that a high voltage pulse is applied and the protection becomes effective; 2) The power dissipation in the protective device is quite large, being given by the product of the input current supplied by the pulse and the limiting voltage of the protective device. Electrostatic discharge is most commonly found to occur during handling and/or manufacture of the integrated circuit; once an integrated circuit has been installed in the apparatus in which it is to be used the risk from electrostatic discharge is drastically reduced by the relatively large capacitances to which each input/output pad is connected and by the fact that a relatively insensitive output provided additional protection to any inputs which it drives. It is consequently the common practice to require extreme care in the handling, testing and installation of integrated circuits with requirements for grounding straps to personnel, humidification controls, special conducting surfaces combined with air ionization etc. All of these are intended to reduce the probability of having charges build to the point that an electronic discharge can happen. Furthermore, the devices in the integrated circuit can usually not protect it from electrostatic discharge during the time that the integrated circuit is being manufactured, i.e., the wafer level.